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ltc2604/ltc2614/ltc2624 1 2604fd block diagram features applications description quad 16-bit rail-to-rail dacs in 16-lead ssop code 0 16384 32768 49152 65535 error (lsb) 2604 ta01 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v 2 15 1 gnd ref lo ref a v outa v outb ref b cs /ld sck v cc ref d v out d v out c ref c sdo sdi 2604 bd 16 3 4 14 dac a dac d 5 7 6 8 10 12 9 13 dac b dac c decode control logic 32-bit shift register clr 11 input register dac register input register input register input register dac register dac register dac register the ltc ? 2604/ltc2614/ltc2624 are quad 16-,14- and 12-bit 2.5v to 5.5v rail-to-rail voltage output dacs in 16-lead narrow ssop packages. these parts have separate reference inputs for each dac. they have built-in high per- formance output buffers and are guaranteed monotonic. these parts establish advanced performance standards for output drive, crosstalk and load regulation in single- supply, voltage output multiples. the parts use a simple spi/microwire compatible 3-wire serial interface which can be operated at clock rates up to 50mhz. daisy-chain capability and a hardware clr function are included. the ltc2604/ltc2614/ltc2624 incorporate a power-on reset circuit. during power-up, the voltage outputs rise less than 10mv above zero scale; and after power-up, they stay at zero scale until a valid write and update take place. the power-on reset circuit resets the ltc2604-1/ltc2614-1 /ltc2624-1 to midscale. the voltage outputs stay at mid- scale until a valid write and update take place. l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n smallest pin compatible quad 16-bit dac: ltc2604: 16-bits ltc2614: 14-bits ltc2624: 12-bits n guaranteed 16-bit monotonic over temperature n separate reference inputs for each dac n wide 2.5v to 5.5v supply range n low power operation: 250a per dac at 3v n individual dac power-down to 1a, max n ultralow crosstalk between dacs (<5v) n high rail-to-rail output drive (15ma) n double buffered digital inputs n ltc2604-1/ltc2614-1/ltc2624-1: power-on reset to midscale n 16-lead narrow ssop package n mobile communications n process control and industrial automation n instrumentation n automatic test equipment differential nonlinearity (ltc2604)
ltc2604/ltc2614/ltc2624 2 2604fd 1 2 3 4 5 6 7 8 top view gn package 16-lead plastic ssop 16 15 14 13 12 11 10 9 gnd ref lo ref a v out a v out b ref b cs /ld sck v cc ref d v out d v out c ref c clr sdo sdi t jmax = 125c, ja = 150c/w absolute maximum ratings pin configuration order information the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref a = ref b = ref c = ref d = 4.096v (v cc = 5v), ref a = ref b = ref c = ref d = 2.048v (v cc = 2.5v), ref lo = 0v, v out unloaded, unless otherwise noted. (note 10) lead free finish tape and reel part marking package description temperature range ltc2604cgn#pbf ltc2604cgn#trpbf 2604 16-lead narrow ssop package 0c to 70c ltc2604cgn-1#pbf ltc2604cgn-1#trpbf 26041 16-lead narrow ssop package 0c to 70c ltc2604ign#pbf ltc2604ign#trpbf 2604i 16-lead narrow ssop package C40c to 85c ltc2604ign-1#pbf ltc2604ign-1#trpbf 2604i1 16-lead narrow ssop package C40c to 85c ltc2614cgn#pbf ltc2614cgn#trpbf 2614 16-lead narrow ssop package 0c to 70c ltc2614cgn-1#pbf ltc2614cgn-1#trpbf 26141 16-lead narrow ssop package 0c to 70c ltc2614ign#pbf ltc2614ign#trpbf 2614i 16-lead narrow ssop package C40c to 85c ltc2614ign-1#pbf ltc2614ign-1#trpbf 2614i1 16-lead narrow ssop package C40c to 85c ltc2624cgn#pbf ltc2624cgn#trpbf 2624 16-lead narrow ssop package 0c to 70c ltc2624cgn-1#pbf ltc2624cgn-1#trpbf 26241 16-lead narrow ssop package 0c to 70c ltc2624ign#pbf ltc2624ign#trpbf 2624i 16-lead narrow ssop package C40c to 85c ltc2624ign-1#pbf ltc2624ign-1#trpbf 2624i1 16-lead narrow ssop package C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics symbol parameter conditions ltc2624/ltc2624-1 ltc2614/ltc2614-1 ltc2604/ltc2604-1 units min typ max min typ max min typ max dc performance resolution l 12 14 16 bits monotonicity (note 2) l 12 14 16 bits dnl differential nonlinearity (note 2) l 0.5 1 1 lsb inl integral nonlinearity (note 2) l 0.9 4 4 16 14 64 lsb any pin to gnd ............................................ C0.3v to 6v any pin to v cc ............................................. C6v to 0.3v maximum junction temperature .......................... 125c operating temperature range ltc2604c/ltc2614c/ltc2624c ............. 0c to 70c ltc2604c-1/ltc2614c-1/ ltc2624c-1 ............................................. 0c to 70c ltc2604i/ltc2614i/ltc2624i .............C40c to 85c ltc2604i-1/ltc2614i-1/ ltc2624i-1 ..........................................C40c to 85c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec)................... 300c (note 1)
ltc2604/ltc2614/ltc2624 3 2604fd symbol parameter conditions min typ max units psr power supply rejection v cc = 5v 10% v cc = 3v 10% C80 C80 db db r out dc output impedance v ref = v cc = 5v, midscale; C15ma i out 15ma v ref = v cc = 2.5v, midscale; C7.5ma i out 7.5ma l l 0.025 0.030 0.15 0.15 dc crosstalk (note 4) due to full scale output change (note 5) due to load current change due to powering down (per channel) 5 1 3.5 v v/ma v i sc short-circuit output current v cc = 5.5v, v ref = 5.5v code: zero scale; forcing output to v cc code: full scale; forcing output to gnd l l 15 15 34 36 60 60 ma ma v cc = 2.5v, v ref = 2.5v code: zero scale; forcing output to v cc code: full scale; forcing output to gnd l l 7.5 7.5 18 24 50 50 ma ma reference input input voltage range l 0v cc a resistance normal mode l 88 128 160 k capacitance 14 pf i ref reference current, power down mode all dacs powered down l 0.001 1 a power supply v cc positive supply voltage for speci? ed performance l 2.5 5.5 v i cc supply current v cc = 5v (note 3) v cc = 3v (note 3) all dacs powered down (note 3) v cc = 5v all dacs powered down (note 3) v cc = 3v l l l l 1.3 1 0.35 0.10 2 1.6 1 1 ma ma a a digital i/o v ih digital input high voltage v cc = 2.5v to 5.5v v cc = 2.5v to 3.6v l l 2.4 2.0 v v electrical characteristics the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref a = ref b = ref c = ref d = 4.096v (v cc = 5v), ref a = ref b = ref c = ref d = 2.048v (v cc = 2.5v), ref lo = 0v, v out unloaded, unless otherwise noted. (note 10) symbol parameter conditions ltc2624/ltc2624-1 ltc2614/ltc2614-1 ltc2604/ltc2604-1 units min typ max min typ max min typ max load regulation v ref = v cc = 5v, midscale i out = 0ma to 15ma sourcing i out = 0ma to 15ma sinking l l 0.025 0.025 0.125 0.125 0.1 0.1 0.5 0.5 0.3 0.3 2 2 lsb/ma lsb/ma v ref = v cc = 2.5v, midscale i out = 0ma to 7.5ma sourcing i out = 0ma to 7.5ma sinking l l 0.05 0.05 0.25 0.25 0.2 0.2 1 1 0.7 0.7 4 4 lsb/ma lsb/ma zse zero-scale error l 1.5 9 1.5 9 1.5 9 mv v os offset error (note 7) l 1.5 9 1.5 9 1.5 9 mv v os temperature coef? cient 5 5 5 v/c ge gain error l 0.1 0.7 0.1 0.7 0.1 0.7 %fsr gain temperature coef? cient 5 5 5 ppm/c the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref a = ref b = ref c = ref d = 4.096v (v cc = 5v), ref a = ref b = ref c = ref d = 2.048v (v cc = 2.5v), ref lo = 0v, v out unloaded, unless otherwise noted. (note 10)
ltc2604/ltc2614/ltc2624 4 2604fd the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref a = ref b = ref c = ref d = 4.096v (v cc = 5v), ref a = ref b = ref c = ref d = 2.048v (v cc = 2.5v), ref lo = 0v, v out unloaded, unless otherwise noted. (note 10) electrical characteristics symbol parameter conditions ltc2624/ltc2624-1 ltc2614/ltc2614-1 ltc2604/ltc2604-1 min typ max min typ max min typ max units ac performance t s settling time (note 8) 0.024% (1lsb at 12 bits) 0.006% (1lsb at 14 bits) 0.0015% (1lsb at 16 bits) 77 9 7 9 10 s s s settling time for 1lsb step (note 9) 0.024% (1lsb at 12 bits) 0.006% (1lsb at 14 bits) 0.0015% (1lsb at 16 bits) 2.7 2.7 4.8 2.7 4.8 5.2 s s s voltage output slew rate 0.80 0.80 0.80 v/s capacitive load driving 1000 1000 1000 pf glitch impulse at midscale transition 12 12 12 nv ? s multiplying bandwidth 180 180 180 khz e n output voltage noise density at f = 1khz at f = 10khz 120 100 120 100 120 100 nv hz nv hz output voltage noise 0.1hz to 10hz 15 15 15 v pCp symbol parameter conditions min typ max units v cc = 2.5v to 5.5v t 1 sdi valid to sck setup l 4ns t 2 sdi valid to sck hold l 4ns t 3 sck high time l 9ns t 4 sck low time l 9ns t 5 cs /ld pulse width l 10 ns t 6 lsb sck high to cs /ld high l 7ns t 7 cs /ld low to sck high l 7ns t 8 sdo propagation delay from sck falling edge c load = 10pf v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v l l 20 45 ns ns t 9 clr pulse width l 20 ns symbol parameter conditions min typ max units v il digital input low voltage v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v l l 0.8 0.6 v v v oh digital output high voltage load current = C100a l v cc C 0.4 v v ol digital output low voltage load current = +100a l 0.4 v i lk digital input leakage v in = gnd to v cc l 1 a c in digital input capacitance (note 6) l 8pf the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref a = ref b = ref c = ref d = 4.096v (v cc = 5v), ref a = ref b = ref c = ref d = 2.048v (v cc = 2.5v), ref lo = 0v, v out unloaded, unless otherwise noted. (note 10) timing characteristics the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref a = ref b = ref c = ref d = 4.096v (v cc = 5v), ref a = ref b = ref c = ref d = 2.048v (v cc = 2.5v), ref lo = 0v, v out unloaded, unless otherwise noted. (note 10)
ltc2604/ltc2614/ltc2624 5 2604fd typical performance characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: linearity and monotonicity are de? ned from code k l to code 2 n C 1, where n is the resolution and k l is given by k l = 0.016(2 n /v ref ), rounded to the nearest whole code. for v ref = 4.096v and n = 16, k l = 256, linearity is de? ned from code 256 to code 65,535. note 3: digital inputs at 0v or v cc . note 4: dc crosstalk is measured with v cc = 5v and v ref = 4.096v, with the measured dac at midscale, unless otherwise noted. note 5: r l = 2k to gnd or v cc . note 6: guaranteed by design and not production tested. note 7: inferred from measurement at code 256 (ltc2604), code 64 (ltc2614) or code 16 (ltc2624), and at full scale. note 8: v cc = 5v, v ref = 4.096v. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 200pf to gnd. note 9: v cc = 5v, v ref = 4.096v. dac is stepped 1lsb between half scale and half scale C1. load is 2k in parallel with 200pf to gnd. note 10: these speci? cations apply to ltc2604/ltc2604-1, ltc2614/ ltc2614-1, ltc2624/ltc2624-1. temperature (c) C50 C30 C10 10 30 50 70 90 offset error (mv) 2604 g03 3 2 1 0 C1 C2 C3 i out (ma) C35 C25 C15 C5 5 15 25 35 v out (mv) 2604 g02 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v ref = v cc = 5v code = midscale v ref = v cc = 3v i out (ma) C40 C30 C20 C10 0 10 20 30 40 v out (v) 2604 g01 0.10 0.08 0.06 0.04 0.02 0 C0.02 C0.04 C0.06 C0.08 C0.10 v ref = v cc = 5v v ref = v cc = 3v v ref = v cc = 5v v ref = v cc = 3v code = midscale current limiting load regulation offset error vs temperature v cc (v) 2.5 3 3.5 4 4.5 5 5.5 offset error (mv) 2604 g06 3 2 1 0 C1 C2 C3 temperature (c) C50 C30 C10 10 30 50 70 90 gain error (%fsr) 2604 g05 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 temperature (c) C50 C30 C10 10 30 50 70 90 zero-scale error (mv) 2604 g04 3 2.5 2.0 1.5 1.0 0.5 0 gain error vs temperature offset error vs v cc zero-scale error vs temperature (ltc2604/ltc2604-1, ltc2614/ltc2614-1, ltc2624/ltc2624-1) the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref a = ref b = ref c = ref d = 4.096v (v cc = 5v), ref a = ref b = ref c = ref d = 2.048v (v cc = 2.5v), ref lo = 0v, v out unloaded, unless otherwise noted. (note 10) timing characteristics symbol parameter conditions min typ max units t 10 cs /ld high to sck positive edge l 7ns sck frequency 50% duty cycle l 50 mhz
ltc2604/ltc2614/ltc2624 6 2604fd logic voltage (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i cc (ma) 2604 g13 2.0 1.8 1.6 1.4 1.2 1.0 0.8 v cc = 5v sweep sck, sdi and cs /ld 0v to v cc supply current vs logic voltage exiting power-down to midscale i out (ma) 0 1 2 3 4 5 6 7 8 910 v out (v) 2604 g12 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5v sourcing 3v sourcing 3v sinking 5v sinking headroom at rails vs output current (ltc2604/ltc2604-1, ltc2614/ltc2614-1, ltc2624/ltc2624-1) v out 10mv/div 250s/div 2604 g11 v cc 1v/div 4mv peak midscale glitch impulse power-on reset glitch power-on reset to midscale v out 10mv/div cs /ld 5v/div 2.5s/div 2604 g10 12nv-s typ v ref = v cc v cc 1v/div v out 1v/div 500s/div 2604 g34 typical performance charateristics 2.5s/div v out 0.5v/div cs /ld 5v/div 2604 g14 v cc = 5v v ref = 2v dacs a-c in power-down mode 2.5s/div v out 0.5v/div 2604 g09 v ref = v cc = 5v 1/4-scale to 3/4-scale v cc (v) 2.5 3 3.5 4 4.5 5 5.5 i cc (na) 2604 g08 450 400 350 300 250 200 150 100 50 0 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 gain error (%fsr) 2604 g07 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 i cc shutdown vs v cc large-signal settling gain error vs v cc
ltc2604/ltc2614/ltc2624 7 2604fd typical performance charateristics v out 1v/div 1s/div 2604 g15 clr 5v/div 1v/div 0 C50 10ma/div C40 C30 C20 C10 0 1 234 2604 g19 56 v cc = 5.5v v ref = 5.6v code = full scale v out swept v cc to 0v 1v/div 0 0 10ma/div 10 20 30 40 50 1 234 2604 g18 56 v cc = 5.5v v ref = 5.6v code = 0 v out swept 0v to v cc v out 10 v/div seconds 012345678910 2604 g17 frequency (hz) 1k db 0 C3 C6 C9 C12 C15 C18 C21 C24 C27 C30 C33 C36 1m 2604 g16 10k 100k v cc = 5v v ref (dc) = 2v v ref (ac) = 0.2v p-p code = full scale hardware clr multiplying frequency response output voltage noise, 0.1hz to 10hz short-circuit output current vs v out (sinking) short-circuit output current vs v out (sourcing) hardware clr to midscale v out 1v/div 1s/div 2604 g35 clr 5v/div v cc = 5v v ref = 4.096v code = full scale temperature (c) C50 C30 C10 10 30 50 70 90 inl (lsb) 2604 g22 32 24 16 8 0 C8 C16 C24 C32 v cc = 5v v ref = 4.096v inl (pos) inl (neg) code 0 16384 32768 49152 65535 dnl (lsb) 2604 g21 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v code 0 16384 32768 49152 65535 inl (lsb) 2604 g20 32 24 16 8 0 C8 C16 C24 C32 v cc = 5v v ref = 4.096v (ltc2604/ltc26041) i n (inl) d n (dnl) inl t (ltc2604/ltc26041 ltc2614/ltc26141 ltc2624/ltc26241)
ltc2604/ltc2614/ltc2624 8 2604fd code 0 4096 8192 12288 16383 dnl (lsb) 2604 g29 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v 2s/div 2604 g30 v out 100v/div cs /ld 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 8.9s code 0 4096 8192 12288 16383 inl (lsb) 2604 g28 8 6 4 2 0 C2 C4 C6 C8 v cc = 5v v ref = 4.096v (ltc2614/ltc2614-1) integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb 5s/div 2604 g27 v out 100v/div cs /ld 2v/div v cc = 5v, v ref = 4.096v code 512 to 65535 step average of 2048 events settling to 1lsb 12.3s 2s/div 2604 g26 v out 100v/div cs /ld 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 9.7s settling to 1lsb settling of full-scale step typical performance charateristics (ltc2604/ltc2604-1) v ref (v) 0 1 2 3 4 5 dnl (lsb) 2604 g25 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 v cc = 5.5v dnl (pos) dnl (neg) v ref (v) 0 1 2 3 4 5 inl (lsb) 2604 g24 32 24 16 8 0 C8 C16 C24 C32 v cc = 5.5v inl (pos) inl (neg) temperature (c) C50 C30 C10 10 30 50 70 90 dnl (lsb) 2604 g23 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v dnl (pos) dnl (neg) dnl vs temperature inl vs v ref dnl vs v ref
ltc2604/ltc2614/ltc2624 9 2604fd pin functions 2s/div 2604 g33 v out 1mv/div cs /ld 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 6.8s code 0 1024 2048 3072 4095 dnl (lsb) 2604 g32 v cc = 5v v ref = 4.096v 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 code 0 1024 2048 3072 4095 inl (lsb) 2604 g31 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 v cc = 5v v ref = 4.096v differential nonlinearity (dnl) settling to 1lsb (ltc2624/ltc2624-1) integral nonlinearity (inl) gnd (pin 1): analog ground. ref lo (pin 2): reference low. the voltage at this pin sets the zero scale (zs) voltage of all dacs. this pin can be raised up to 1v above ground at v cc = 5v or 100mv above ground at v cc = 3v. ref a, ref b, ref c, ref d (pins 3, 6, 12, 15): refer- ence voltage inputs for each dac. ref x sets the full scale voltage of the dacs. 0v ref x v cc . v out a to v out d (pins 4, 5, 13, 14): dac analog voltage outputs. the output range is from ref lo to ref x. cs /ld (pin 7): serial interface chip select/load input. when cs /ld is low, sck is enabled for shifting data on sdi into the register. when cs /ld is taken high, sck is disabled and the speci? ed command (see table 1) is executed. sck (pin 8): serial interface clock input. cmos and ttl compatible. sdi (pin 9): serial interface data input. data is applied to sdi for transfer to the device at the rising edge of sck. the ltc2604/ltc2604-1, ltc2614/ltc2614-1, ltc2624/ ltc2624-1 accept input word lengths of either 24 or 32 bits. sdo (pin 10): serial interface data output. this pin is used for daisy-chain operation. the serial output of the shift register appears at the sdo pin. the data transferred to the device via the sdi pin is delayed 32 sck rising edges before being output at the next falling edge. sdo is an active output and does not go high impedance, even when cs/ld is taken to a logic high level. clr (pin 11): asynchronous clear input. a logic low at this level-triggered input clears all registers and causes the dac voltage outputs to drop to 0v for the ltc2604/ ltc2614/ltc2624. a logic low at this input sets all registers to midscale code and causes the dac voltage outputs to go to midscale for the ltc2604-1/ltc2614-1/ltc2624-1. cmos and ttl compatible. v cc (pin 16): supply voltage input. 2.5v v cc 5.5v. typical performance charateristics
ltc2604/ltc2614/ltc2624 10 2604fd timing diagram outputs from the dac during this time. the ltc2604/ ltc2614/ltc2624 contain circuitry to reduce the power- on glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. for example, if the power supply is ramped to 5v in 1ms, the analog outputs rise less than 10mv above ground (typ) during power-on. see power-on reset glitch in the typical performance characteristics section. power-on reset the ltc2604/ltc2614/ltc2624 clear the outputs to zero scale when power is ? rst applied, making system initialization consistent and repeatable. the ltc2604-1/ ltc2614-1/ltc2624-1 set the voltage outputs to midscale when power is ? rst applied. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero sdi sdo c s /ld sck 2604 f01 t 2 t 8 t 10 t 5 t 7 t 6 t 1 t 3 t 4 123 23 24 operation figure 1 2 15 1 gnd ref lo ref a v outa v outb ref b cs /ld sck v cc ref d v out d v out c ref c sdo sdi 2604 bd 16 3 4 14 dac a dac d 5 7 6 8 10 12 9 13 dac b dac c decode control logic 32-bit shift register clr 11 input register dac register input register input register input register dac register dac register dac register block diagram
ltc2604/ltc2614/ltc2624 11 2604fd operation c3 command address data (12 bits + 4 dont-care bits) c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x xx 2604 tbl03 msb lsb c3 command address data (14 bits + 2 dont-care bits) c2 c1 c0 a3 a2 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x 2604 tbl02 msb lsb c3 command address data (16 bits) c2 c1 c0 a3 a2 a1 a0 d13 d14 d15 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 2604 tbl01 msb lsb input word (ltc2604) input word (ltc2614) input word (ltc2624) power supply sequencing the voltage at ref (pins 3, 6, 12 and 15) should be kept within the range C 0.3v ref x v cc + 0.3v (see abso- lute maximum ratings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 16) is in transition. transfer function the digital-to-analog transfer function is v out(ideal) = k 2 n [ref x C ref lo] + ref lo where k is the decimal equivalent of the binary dac input code, n is the resolution and ref x is the voltage at ref a, ref b, ref c and ref d (pins 3, 6, 12 and 15). serial interface the cs /ld input is level triggered. when this input is taken low, it acts as a chip-select signal, powering-on the sdi and sck buffers and enabling the input shift register. data (sdi input) is transferred at the next 24 rising sck edges. the 4-bit command, c3-c0, is loaded ? rst; then the 4-bit dac address, a3-a0; and ? nally the 16-bit data word. the data word comprises the 16-, 14- or 12-bit input code, ordered msb-to-lsb, followed by 0, 2 or 4 dont-care bits (ltc2604, ltc2614 and ltc2624 respectively). data can only be transferred to the device when the cs /ld signal is low. the rising edge of cs /ld ends the data transfer and causes the device to carry out the action speci? ed in the 24-bit input word. the complete sequence is shown in figure 2a. the command (c3-c0) and address (a3-a0) assignments are shown in table 1. the ? rst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected dac, n. an update table 1. command* c3 c2 c1 c0 0 0 0 0 write to input register n 0 0 0 1 update (power up) dac register n 0 0 1 0 write to input register n, update (power up) all n 0 0 1 1 write to and update (power up) n 0 1 0 0 power down n 1 1 1 1 no operation address (n)* a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 1 1 1 1 all dacs *command and address codes not shown are reserved and should not be used.
ltc2604/ltc2614/ltc2624 12 2604fd operation operation copies the data word from the input register to the dac register. once copied into the dac register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the dac output. the update operation also powers up the selected dac if it had been in power-down mode. the data path and registers are shown in the block diagram. while the minimum input word is 24 bits, it may optionally be extended to 32 bits. to use the 32-bit word width, 8 dont-care bits are transferred to the device ? rst, followed by the 24-bit word as just described. figure 2b shows the 32-bit sequence. the 32-bit word is required for daisy- chain operation, and is also available to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). daisy-chain operation the serial output of the shift register appears at the sdo pin. data transferred to the device from the sdi input is delayed 32 sck rising edges before being output at the next sck falling edge. the sdo output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., sck, sdi and cs /ld). such a daisy-chain series is con? gured by connecting sdo of each upstream device to sdi of the next device in the chain. the shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the ? rst instruction addresses the last device in the chain and so forth. the sck and cs /ld signals are common to all devices in the series. in use, cs /ld is ? rst taken low. then the concatenated input data is transferred to the chain, using sdi of the ? rst device as the data input. when the data transfer is complete, cs /ld is taken high, completing the instruction sequence for all devices simultaneously. a single device can be controlled by using the no-operation command (1111) for the other devices in the chain. power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four outputs are needed. when in power-down, the buffer ampli? ers, bias circuits and reference inputs are disabled, and draw essentially zero current. the dac outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 90k resis- tors. input- and dac-register contents are not disturbed during power-down. any channel or combination of channels can be put into power-down mode by using command 0100 b in combi- nation with the appropriate dac address, (n). the 16-bit data word is ignored. the supply current is reduced by approximately 1/4 for each dac powered down. the ef- fective resistance at ref x (pins 3, 6, 12 and 15) are at high-impedance input (typically > 1g) when the cor- responding dacs are powered down. normal operation can be resumed by executing any com- mand which includes a dac update, as shown in table 1. the selected dac is powered up as its voltage output is updated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if less than four dacs are in a powered-down state prior to the update command, the power-up delay time is 5s. if on the other hand, all four dacs are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual dac ampli? ers and reference inputs. in this case, the power up delay time is 12s (for v cc = 5v) or 30s (for v cc = 3v). voltage outputs each of the four rail-to-rail ampli? ers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the ampli? ers ability to maintain the rated voltage accuracy over a wide range of load conditions. the measured change in output voltage per milliampere of forced load current change is expressed in lsb/ma.
ltc2604/ltc2614/ltc2624 13 2604fd operation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 cs /ld sck sdi command word address word data word 24-bit input word 2604 f02a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x cs /ld sck sdi command word address word data word dont care c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x sdo current 32-bit input word 2604 f02b previous 32-bit input word t 2 t 3 t 4 t 1 t 8 d15 17 sck sdi sdo previous d14 previous d15 18 d14 figure 2a. ltc2604 24-bit load sequence (minimum input word) ltc2614 sdi data word: 14-bit input code + 2 dont care bits ltc2624 sdi data word: 12-bit input code + 4 dont care bits figure 2b. ltc2604 32-bit load sequence ltc2614 sdi/sdo data word: 14-bit input code + 2 dont care bits ltc2624 sdi/sdo data word: 12-bit input code + 4 dont care bits
ltc2604/ltc2614/ltc2624 14 2604fd operation 2600 f03 input code output voltage negative offset 0v 32,768 0 65,535 input code output voltage v ref = v cc v ref = v cc input code output voltage positive fse figure 3. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero scale (c) effect of positive full-scale error for codes near full scale (b) (a) (c) dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the ampli? ers dc output impedance is 0.025 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 30 ? 1ma = 30mv. see the graph headroom at rails vs output current in the typical performance characteristics section. the ampli? ers are stable driving capacitive loads of up to 1000pf. board layout the excellent load regulation and dc crosstalk performance of these devices is achieved in part by keeping signal and power grounds separate. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the devices ground pin as possible. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin functions as a return path for power sup- ply currents in the device and should be connected to analog ground. resistance from the gnd pin to system star ground should be as low as possible. when a zero scale dac output voltage of zero is desired, the reflo pin (pin 2) should be connected to system star ground. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in figure 3b. similarly, limiting can occur near full scale when the ref pins are tied to v cc . if ref x = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 3c. no full-scale limiting can occur if ref x is less than v cc C fse. offset and linearity are de? ned and tested over the region of the dac transfer function where no output limiting can occur.
ltc2604/ltc2614/ltc2624 15 2604fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale package description gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641)
ltc2604/ltc2614/ltc2624 16 2604fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0309 rev d ? printed in usa related parts part number description comments ltc1458/ltc1458l quad 12-bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.096v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1654 dual 14-bit rail-to-rail v out dac programmable speed/power ltc1655/ltc1655l single 16-bit v out dac with serial interface in so-8 v cc = 5v(3v), low power, deglitched ltc1657/ltc1657l parallel 5v/3v 16-bit v out dac low power, deglitched, rail-to-rail v out ltc1660/ltc1665 octal 8-bit/10-bit v out dac in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1821 parallel 16-bit voltage output dac precision 16-bit settling in 2s for 10v step ltc2600/ltc2610/ltc2620 octal 16-bit/14-bit/12-bit rail-to-rail dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range ltc2602/ltc2612/ltc2622 dual 16-bit/14-bit/12-bit rail-to-rail dacs in 8-lead msop 300a per dac, 2.5v to 5.5v supply range typical application 0 90 i + q modulator rf lo q input i input 5v 5v 5v 5v 70mhz in out 1k 10k 10k 1k 10k 10k 20k 0.1f 0.01f 0.01f 20 49.9 49.9 49.9 zc830 zc830 47pf 10pf 20pf *zetex (516) 543-7100 optional 5v 5v ltc2604 cs/ld sck sdi dac d dac b optional dac c dac a 0.1f 0.1f 20k 100k 2.74k 1% 2.74k 1% 2.74k 1% 2.74k 1% 100k 2.74k 1% 2.74k 1% 2.74k 1% 2.74k 1% 0.1f 2604 f04 figure 4. using dac a and dac b for nearly continuous attenuation control and dac c and dac d to trim for minimum lo feedthrough in a mixer

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